EHCI Controller Registers (D29:F0, D26:F0)
658 Datasheet
16.1.30 ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 80h Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
16.1.31 EHCIIR1—EHCI Initialization Register 1
(USB EHCI—D29:F0, D26:F0)
Address Offset: 84h Attribute: R/W
Default Value: 01h Size: 32 bits
3
SMI on Periodic Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller
will issue an SMI.
2
SMI on CF Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will
issue an SMI.
1
SMI on HCHalted Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host
controller will issue an SMI.
0
SMI on HCReset Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller
will issue an SMI.
Bit Description
Bit Description
7:1 Reserved
0
WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally
read-only registers in the EHC function to be written by software. Registers that
may only be written when this mode is entered are noted in the summary tables
and detailed description as “Read/Write-Special”. The registers fall into two
categories:
1. System-configured parameters
2. Status bits
Bit Description
31:5 Reserved
4
Pre-fetch Based Pause Enable — R/W.
0 = Pre-fetch Based Pause is disabled.
1 = Pre-fetch Based Pause is enabled.
3:0 Reserved
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