Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 659

Datasheet 659
EHCI Controller Registers (D29:F0, D26:F0)
16.1.32 FLR_CID—Function Level Reset Capability ID
(USB EHCI—D29:F0, D26:F0)
Address Offset: 98h Attribute: RO
Default Value: 09h Size: 8 bits
Function Level Reset: No
16.1.33 FLR_NEXT—Function Level Reset Next Capability Pointer
(USB EHCI—D29:F0, D26:F0)
Address Offset: 99h Attribute: RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
16.1.34 FLR_CLV—Function Level Reset Capability Length and
Version
(USB EHCI—D29:F0, D26:F0)
Address Offset: 9Ah–9Bh Attribute: R/WO, RO
Default Value: 2006h Size: 16 bits
Function Level Reset: No
When FLRCSSEL = 0, this register is defined as follows:
When FLRCSSEL = 1, this register is defined as follows:
Bit Description
7:0
Capability ID — RO.
13h = If FLRCSSEL = 0
09h (Vendor Specific Capability) = If FLRCSSEL = 1
Bit Description
7:0 A value of 00h in this register indicates this is the last capability field.
Bit Description
15:10 Reserved.
9
FLR Capability — R/WO.
1 = Support for Function Level Reset (FLR).
8
TXP Capability — R/WO.
1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is
supported.
7:0
Capability Length — RO. This field indicates the # of bytes of this vendor specific
capability as required by the PCI specification. It has the value of 06h for the FLR
capability.
Bit Description
15:12
Vendor Specific Capability ID — RO. A value of 2h in this field identifies this
capability as Function Level Reset.
11:8 Capability Version — RO. This field indicates the version of the FLR capability.
7:0
Capability Length — RO. This field indicates the # of bytes of this vendor specific
capability as required by the PCI specification. It has the value of 06h for the FLR
capability.