EHCI Controller Registers (D29:F0, D26:F0)
672 Datasheet
16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment
Register
Offset: MEM_BASE + 30h–33h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
This 32-bit register corresponds to the most significant address bits [63:32] for all
EHCI data structures. Since the PCH hardwires the 64-bit Addressing Capability field in
HCCPARAMS to 1, this register is used with the link pointers to construct 64-bit
addresses to EHCI control data structures. This register is concatenated with the link
pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data
structure link field to construct a 64-bit address. This register allows the host software
to locate all control data structures within the same 4 GB memory segment.
16.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
Register
Offset: MEM_BASE + 34h–37h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. Since the PCH host controller operates in 64-bit mode (as indicated by
the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset 08h,
bit 0), then the most significant 32 bits of every control data structure address comes
from the CTRLDSSEGMENT register. HCD loads this register prior to starting the
schedule execution by the host controller. The memory structure referenced by this
physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this
register are combined with the Frame Index Register (FRINDEX) to enable the Host
controller to step through the Periodic Frame List in sequence.
Bit Description
31:12
Upper Address[63:44] — RO. Hardwired to 0s. The PCH EHC is only capable of
generating addresses up to 16 terabytes (44 bits of address).
11:0
Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32
when forming a control data structure address.
Bit Description
31:12
Base Address (Low) — R/W. These bits correspond to memory address signals
[31:12], respectively.
11:0 Reserved.
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