Integrated Intel
®
High Definition Audio Controller Registers
694 Datasheet
17.1.1.24 PC—Power Management Capabilities Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 52h–53h Attribute: RO
Default Value: C842h Size: 16 bits
17.1.1.25 PCS—Power Management Control and Status Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 54h–57h Attribute: RO, R/W, R/WC
Default Value: 00000000h Size: 32 bits
Function Level Reset: No
Bit Description
15:11
PME Support — RO. Hardwired to 11001b. Indicates PME# can be generated from D3
and D0 states.
10 D2 Support — RO. Hardwired to 0. Indicates that D2 state is not supported.
9 D1 Support —RO. Hardwired to 0. Indicates that D1 state is not supported.
8:6
Aux Current — RO. Hardwired to 001b. Reports 55 mA maximum suspend well current
required when in the D3
COLD
state.
5
Device Specific Initialization (DSI) — RO. Hardwired to 0. Indicates that no device
specific initialization is required.
4 Reserved
3 PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.
2:0
Version — RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power
Management Specification.
Bit Description
31:24 Data — RO. Does not apply. Hardwired to 0.
23 Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0.
22 B2/B3 Support — RO. Does not apply. Hardwired to 0.
21:16 Reserved.
15
PME Status (PMES) — R/WC.
0 = Software clears the bit by writing a 1 to it.
1 = This bit is set when the Intel
®
High Definition Audio controller would normally
assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this
register).
This bit is in the resume well and is cleared by a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
14:9 Reserved
8
PME Enable (PMEE) — R/W.
0 = Disable
1 = When set and if corresponding PMES also set, the Intel
®
High Definition Audio
controller sets the PME_B0_STS bit in the GPE0_STS register (PMBASE +28h).
This bit is in the resume well and is cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
7:2 Reserved
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