Datasheet 7
5.18.1 EHC Initialization.................................................................................. 204
5.18.1.1 BIOS Initialization................................................................... 204
5.18.1.2 Driver Initialization ................................................................. 204
5.18.1.3 EHC Resets............................................................................ 204
5.18.2 Data Structures in Main Memory............................................................. 204
5.18.3 USB 2.0 Enhanced Host Controller DMA................................................... 205
5.18.4 Data Encoding and Bit Stuffing............................................................... 205
5.18.5 Packet Formats.................................................................................... 205
5.18.6 USB 2.0 Interrupts and Error Conditions.................................................. 205
5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ................................ 206
5.18.7 USB 2.0 Power Management.................................................................. 206
5.18.7.1 Pause Feature ........................................................................ 206
5.18.7.2 Suspend Feature..................................................................... 206
5.18.7.3 ACPI Device States ................................................................. 206
5.18.7.4 ACPI System States ................................................................ 207
5.18.8 USB 2.0 Legacy Keyboard Operation....................................................... 207
5.18.9 USB 2.0 Based Debug Port .................................................................... 207
5.18.9.1 Theory of Operation ............................................................... 208
5.18.10EHCI Caching....................................................................................... 212
5.18.11Intel
®
USB Pre-Fetch Based Pause ......................................................... 212
5.18.12Function Level Reset Support (FLR) ........................................................ 212
5.18.12.1FLR Steps.............................................................................. 212
5.18.13USB Overcurrent Protection ................................................................... 213
5.19 Integrated USB 2.0 Rate Matching Hub .............................................................. 214
5.19.1 Overview ............................................................................................ 214
5.19.2 Architecture......................................................................................... 214
5.20 SMBus Controller (D31:F3)............................................................................... 215
5.20.1 Host Controller..................................................................................... 215
5.20.1.1 Command Protocols ................................................................ 216
5.20.2 Bus Arbitration..................................................................................... 219
5.20.3 Bus Timing.......................................................................................... 220
5.20.3.1 Clock Stretching ..................................................................... 220
5.20.3.2 Bus Time Out (The PCH as SMBus Master) ................................. 220
5.20.4 Interrupts / SMI#................................................................................. 220
5.20.5 SMBALERT# ........................................................................................ 221
5.20.6 SMBus CRC Generation and Checking...................................................... 221
5.20.7 SMBus Slave Interface .......................................................................... 222
5.20.7.1 Format of Slave Write Cycle ..................................................... 222
5.20.7.2 Format of Read Command........................................................ 224
5.20.7.3 Slave Read of RTC Time Bytes.................................................. 226
5.20.7.4 Format of Host Notify Command............................................... 227
5.21 Thermal Management ...................................................................................... 228
5.21.1 Thermal Sensor ................................................................................... 228
5.21.1.1 Internal Thermal Sensor Operation............................................ 228
5.21.2 Thermal Reporting Over System Management Link 1 Interface (SMLink1) .... 229
5.21.2.1 Supported Addresses............................................................... 230
5.21.2.2 I
2
C Write Commands to the Intel
®
ME....................................... 231
5.21.2.3 Block Read Command.............................................................. 231
5.21.2.4 Read Data Format................................................................... 233
5.21.2.5 Thermal Data Update Rate....................................................... 233
5.21.2.6 Temperature Comparator and Alert ........................................... 233
5.21.2.7 BIOS Set Up........................................................................... 235
5.21.2.8 SMBus Rules .......................................................................... 235
5.21.2.9 Case for Considerations........................................................... 236
5.22 Intel
®
High Definition Audio Overview (D27:F0) .................................................. 238
5.22.1 Intel
®
High Definition Audio Docking (Mobile Only)................................... 238
5.22.1.1 Dock Sequence....................................................................... 238
5.22.1.2 Exiting D3/CRST# When Docked............................................... 239
5.22.1.3 Cold Boot/Resume from S3 When Docked .................................. 240
5.22.1.4 Undock Sequence ................................................................... 240
5.22.1.5 Normal Undock....................................................................... 240
5.22.1.6 Surprise Undock ..................................................................... 241
5.22.1.7 Interaction between Dock/Undock and Power Management States. 241
5.22.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# ............. 241
5.23 Intel
®
ME and Intel
®
ME Firmware 7.0............................................................... 242
5.24 Serial Peripheral Interface (SPI)........................................................................ 242
5.24.1 SPI Supported Feature Overview............................................................ 242
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