8 Datasheet
5.24.1.1 Non-Descriptor Mode ...............................................................242
5.24.1.2 Descriptor Mode......................................................................243
5.24.2 Flash Descriptor ...................................................................................244
5.24.2.1 Descriptor Master Region .........................................................246
5.24.3 Flash Access ........................................................................................247
5.24.3.1 Direct Access Security..............................................................247
5.24.3.2 Register Access Security ..........................................................247
5.24.4 Serial Flash Device Compatibility Requirements ........................................247
5.24.4.1 PCH SPI Based BIOS Requirements............................................248
5.24.4.2 Integrated LAN Firmware SPI Flash Requirements........................248
5.24.4.3 Intel
®
Management Engine Firmware SPI Flash Requirements.......248
5.24.4.4 Hardware Sequencing Requirements..........................................249
5.24.5 Multiple Page Write Usage Model.............................................................250
5.24.5.1 Soft Flash Protection................................................................250
5.24.5.2 BIOS Range Write Protection ....................................................251
5.24.5.3 SMI# Based Global Write Protection...........................................251
5.24.6 Flash Device Configurations ...................................................................251
5.24.7 SPI Flash Device Recommended Pinout....................................................252
5.24.8 Serial Flash Device Package ...................................................................252
5.24.8.1 Common Footprint Usage Model................................................252
5.24.8.2 Serial Flash Device Package Recommendations ...........................253
5.25 Feature Capability Mechanism ...........................................................................253
5.26 PCH Display Interfaces .....................................................................................254
5.26.1 Analog Display Interface Characteristics...................................................254
5.26.1.1 Integrated RAMDAC.................................................................255
5.26.1.2 DDC (Display Data Channel).....................................................255
5.26.2 Digital Display Interfaces.......................................................................255
5.26.2.1 LVDS (Mobile only)..................................................................255
5.26.2.2 High Definition Multimedia Interface ..........................................258
5.26.2.3 Digital Video Interface (DVI).....................................................259
5.26.2.4 Display Port*..........................................................................259
5.26.2.5 Embedded DisplayPort .............................................................260
5.26.2.6 DisplayPort Aux Channel ..........................................................260
5.26.2.7 DisplayPort Hot-Plug Detect (HPD).............................................260
5.26.2.8 Integrated Audio over HDMI and DisplayPort...............................260
5.26.2.9 Serial Digital Video Out (SDVO).................................................260
5.26.3 Mapping of Digital Display Interface Signals .............................................262
5.26.4 Multiple Display Configurations...............................................................263
5.26.5 High-bandwidth Digital Content Protection (HDCP) ....................................263
5.26.6 Intel
®
Flexible Display Interconnect ........................................................264
5.27 Intel
®
Virtualization Technology ........................................................................264
5.27.1 Intel
®
VT-d Objectives ..........................................................................264
5.27.2 Intel
®
VT-d Features Supported..............................................................264
5.27.3 Support for Function Level Reset (FLR) in PCH..........................................265
5.27.4 Virtualization Support for PCH’s IOxAPIC..................................................265
5.27.5 Virtualization Support for High Precision Event Timer (HPET) ......................265
6 Ballout Definition...................................................................................................267
6.1 Desktop PCH Ballout ........................................................................................267
6.2 Mobile PCH Ballout...........................................................................................279
7 Package Information .............................................................................................293
7.1 Desktop PCH package ......................................................................................293
7.2 Mobile PCH Package.........................................................................................295
8 Electrical Characteristics........................................................................................297
8.1 Thermal Specifications......................................................................................297
8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP)................297
8.1.2 Mobile Storage Specifications and Thermal Design Power (TDP) ..................297
8.2 Absolute Maximum Ratings ...............................................................................298
8.3 PCH Power Supply Range..................................................................................299
8.4 General DC Characteristics................................................................................299
8.5 Display DC Characteristics ................................................................................312
8.6 AC Characteristics............................................................................................314
8.7 Power Sequencing and Reset Signal Timings........................................................331
8.8 Power Management Timing Diagrams .................................................................334
8.9 AC Timing Diagrams.........................................................................................339