Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 701
Integrated Intel
®
High Definition Audio Controller Registers
17.1.1.40 PVCSTS—Port VC Status Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 10Eh–10Fh Attribute: RO
Default Value: 0000h Size: 16 bits
17.1.1.41 VC0CAP—VC0 Resource Capability Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 110h–113h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
15:1 Reserved.
0
VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not
present.
Bit Description
31:24
Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for
endpoint devices
23 Reserved.
22:16
Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
15
Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
14
Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
13:8 Reserved.
7:0
Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for endpoint
devices.