Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 705
Integrated Intel
®
High Definition Audio Controller Registers
17.1.1.49 L1DESC—Link 1 Description Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 140h–143h Attribute: RO
Default Value: 00000001h Size: 32 bits
17.1.1.50 L1ADDL—Link 1 Lower Address Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 148h–14Bh Attribute: RO
Default Value: See Register Description Size: 32 bits
17.1.1.51 L1ADDU—Link 1 Upper Address Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 14Ch–14Fh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:24
Target Port Number — RO. The Intel
®
High Definition Audio controller targets the
PCH’s Port 0.
23:16
Target Component ID — RO. This field returns the value of the ESD.CID field of the
chip configuration section. ESD.CID is programmed by BIOS.
15:2 Reserved.
1 Link Type — RO. Hardwired to 0 indicating Type 0.
0 Link Valid — RO. Hardwired to 1.
Bit Description
31:14
Link 1 Lower Address — RO. Hardwired to match the RCBA register value in the PCI-
LPC bridge (D31:F0:F0h).
13:0 Reserved.
Bit Description
31:0 Link 1 Upper Address — RO. Hardwired to 00000000h.