Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 707

Datasheet 707
Integrated Intel
®
High Definition Audio Controller Registers
5Ah–5Bh RINTCNT Response Interrupt Count 0000h R/W
5Ch RIRBCTL RIRB Control 00h R/W
5Dh RIRBSTS RIRB Status 00h R/WC
5Eh RIRBSIZE RIRB Size 42h RO
60h–63h IC Immediate Command 00000000h R/W
64h–67h IR Immediate Response 00000000h RO
68h–69h IRS Immediate Command Status 0000h
R/W, R/
WC
70h–73h DPLBASE DMA Position Lower Base Address 00000000h R/W, RO
74h–77h DPUBASE DMA Position Upper Base Address 00000000h R/W
80–82h ISD0CTL
Input Stream Descriptor 0 (ISD0)
Control
040000h R/W, RO
83h ISD0STS ISD0 Status 00h R/WC, RO
84h–87h ISD0LPIB ISD0 Link Position in Buffer 00000000h RO
88h–8Bh ISD0CBL ISD0 Cyclic Buffer Length 00000000h R/W
8Ch–8Dh ISD0LVI ISD0 Last Valid Index 0000h R/W
8Eh–8F ISD0FIFOW ISD0 FIFO Watermark 0004h R/W
90h–91h ISD0FIFOS ISD0 FIFO Size 0000h R/W
92h–93h ISD0FMT ISD0 Format 0000h R/W
98h–9Bh ISD0BDPL
ISD0 Buffer Descriptor List Pointer –
Lower Base Address
00000000h R/W, RO
9Ch–9Fh ISD0BDPU
ISD0 Buffer Description List Pointer –
Upper Base Address
00000000h R/W
A0h–A2h ISD1CTL
Input Stream Descriptor 1(ISD01)
Control
040000h R/W, RO
A3h ISD1STS ISD1 Status 00h R/WC, RO
A4h–A7h ISD1LPIB ISD1 Link Position in Buffer 00000000h RO
A8h–ABh ISD1CBL ISD1 Cyclic Buffer Length 00000000h R/W
ACh–ADh ISD1LVI ISD1 Last Valid Index 0000h R/W
AEh–AFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W
B0h–B1h ISD1FIFOS ISD1 FIFO Size 0000h R/W
B2h–B3h ISD1FMT ISD1 Format 0000h R/W
B8h–BBh ISD1BDPL
ISD1 Buffer Descriptor List Pointer –
Lower Base Address
00000000h R/W, RO
BCh–BFh ISD1BDPU
ISD1 Buffer Description List Pointer –
Upper Base Address
00000000h R/W
C0h–C2h ISD2CTL
Input Stream Descriptor 2 (ISD2)
Control
040000h R/W, RO
C3h ISD2STS ISD2 Status 00h R/WC, RO
Table 17-2. Intel
®
High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel
®
High Definition Audio D27:F0) (Sheet 2 of 4)
HDBAR +
Offset
Mnemonic Register Name Default Access