Datasheet 719
Integrated Intel
®
High Definition Audio Controller Registers
17.1.2.20 CORBCTL—CORB Control Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Ch Attribute: R/W
Default Value: 00h Size: 8 bits
17.1.2.21 CORBST—CORB Status Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Dh Attribute: R/WC
Default Value: 00h Size: 8 bits
17.1.2.22 CORBSIZE—CORB Size Register
Intel
®
High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Eh Attribute: RO
Default Value: 42h Size: 8 bits
Bit Description
7:2 Reserved.
1
Enable CORB DMA Engine — R/W.
0 = DMA stop
1 = DMA run
After software writes a 0 to this bit, the hardware may not stop immediately. The
hardware will physically update the bit to 0 when the DMA engine is truly stopped.
Software must read a 0 from this bit to verify that the DMA engine is truly stopped.
0
CORB Memory Error Interrupt Enable — R/W.
If this bit is set, the controller will generate an interrupt if the CMEI status bit (HDBAR
+ 4Dh: bit 0) is set.
Bit Description
7:1 Reserved.
0
CORB Memory Error Indication (CMEI) — R/WC.
1 = Controller detected an error in the path way between the controller and memory.
This may be an ECC bit error or any other type of detectable data error which
renders the command data fetched invalid.
Software can clear this bit by writing a 1 to it. However, this type of error leaves the
audio subsystem in an un-viable state and typically requires a controller reset by
writing a 0 to the Controller Reset # bit (HDBAR + 08h: bit 0).
Bit Description
7:4
CORB Size Capability — RO. Hardwired to 0100b indicating that the PCH only
supports a CORB size of 256 CORB entries (1024B)
3:2 Reserved.
1:0 CORB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B)
To Next Page
Loading...