Integrated Intel
®
High Definition Audio Controller Registers
724 Datasheet
17.1.2.33 DPLBASE—DMA Position Lower Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 70h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
17.1.2.34 DPUBASE—DMA Position Upper Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 74h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:7
DMA Position Lower Base Address — R/W. Lower 32 bits of the DMA Position Buffer
Base Address. This register field must not be written when any DMA engine is running
or the DMA transfer may be corrupted. This same address is used by the Flush Control
and must be programmed with a valid value before the Flush Control bit
(HDBAR+08h:bit 1) is set.
6:1
DMA Position Lower Base Unimplemented bits — RO. Hardwired to 0 to force the 128-
byte buffer alignment for cache line write optimizations.
0
DMA Position Buffer Enable — R/W.
1 = Controller will write the DMA positions of each of the DMA engines to the buffer in
the main memory periodically (typically once per frame). Software can use this
value to know what data in memory is valid data.
Bit Description
31:0
DMA Position Upper Base Address — R/W. Upper 32 bits of the DMA Position Buffer
Base Address. This register field must not be written when any DMA engine is running
or the DMA transfer may be corrupted.
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