Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Integrated Intel
®
High Definition Audio Controller Registers
732 Datasheet
17.1.2.44 SDBDPL—Stream Descriptor Buffer Descriptor List
Pointer Lower Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 98h Attribute: R/W,RO
Input Stream[1]: HDBAR + B8h
Input Stream[2]: HDBAR + D8h
Input Stream[3]: HDBAR + F8h
Output Stream[0]: HDBAR + 118h
Output Stream[1]: HDBAR + 138h
Output Stream[2]: HDBAR + 158h
Output Stream[3]: HDBAR + 178h
Default Value: 00000000h Size: 32 bits
17.1.2.45 SDBDPU—Stream Descriptor Buffer Descriptor List
Pointer Upper Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 9Ch Attribute:R/W
Input Stream[1]: HDBAR + BCh
Input Stream[2]: HDBAR + DCh
Input Stream[3]: HDBAR + FCh
Output Stream[0]: HDBAR + 11Ch
Output Stream[1]: HDBAR + 13Ch
Output Stream[2]: HDBAR + 15Ch
Output Stream[3]: HDBAR + 17Ch
Default Value: 00000000h Size: 32 bits
Bit Description
31:7
Buffer Descriptor List Pointer Lower Base Address — R/W. Lower address of the
Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA
transfer may be corrupted.
6:0 Hardwired to 0 forcing alignment on 128-B boundaries.
Bit Description
31:0
Buffer Descriptor List Pointer Upper Base Address — R/W. Upper 32-bit address
of the Buffer Descriptor List. This value should only be modified when the RUN bit is 0,
or DMA transfer may be corrupted.

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General

Brand	Intel
Model	6 SERIES CHIPSET - DATASHEET 01-2011
Category	Controller
Language	English