SMBus Controller Registers (D31:F3)
742 Datasheet
18.1.6 PI—Programming Interface Register (SMBus—D31:F3)
Offset Address: 09h Attribute: RO
Default Value: 00h Size: 8 bits
18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)
Address Offset: 0Ah Attributes: RO
Default Value: 05h Size: 8 bits
18.1.8 BCC—Base Class Code Register (SMBus—D31:F3)
Address Offset: 0Bh Attributes: RO
Default Value: 0Ch Size: 8 bits
18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0
(SMBus—D31:F3)
Address Offset: 10–13h Attributes: R/W, RO
Default Value: 00000004h Size: 32 bits
Bit Description
7:0 Reserved
Bit Description
7:0
Sub Class Code (SCC) — RO.
05h = SMBus serial controller
Bit Description
7:0
Base Class Code (BCC) — RO.
0Ch = Serial controller.
Bit Description
31:8
Base Address — R/W. Provides the 32 byte system memory base address for the PCH
SMB logic.
7:4 Reserved
3
Prefetchable (PREF) — RO. Hardwired to 0. Indicates that SMBMBAR is not pre-
fetchable.
2:1
Address Range (ADDRNG) — RO. Indicates that this SMBMBAR can be located
anywhere in 64 bit address space. Hardwired to 10b.
0
Memory Space Indicator — RO. This read-only bit always is 0, indicating that the
SMB logic is Memory mapped.
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