Intel 6 SERIES CHIPSET - DATASHEET 01-2011

SMBus Controller Registers (D31:F3)
756 Datasheet
18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 16h Attribute: RO
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 17h Attribute: RO
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
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Bit Description
7:0
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit
0) is set to 1.
Bit Description
7:0
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit
0) is set to 1.