Datasheet 755
SMBus Controller Registers (D31:F3)
18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 11h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
18.2.17 NOTIFY_DADDR—Notify Device Address Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 14h Attribute: RO
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
7:2 Reserved
2
SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the
SMBALERT# source. This bit is logically inverted and ANDed with the
SMBALERT_STS bit (offset SMB_BASE + 00h, bit 5). The resulting signal is
distributed to the SMI# and/or interrupt generation logic. This bit does not effect
the wake logic.
1
HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a
Host Notify command as a wake event. When enabled this event is “OR’d" in with the
other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General
Purpose Event 0 Status register.
0 = Disable
1 = Enable
0
HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation
of interrupt or SMI# when HOST_NOTIFY_STS (offset SMB_BASE + 10h, bit 0) is 1.
This enable does not affect the setting of the HOST_NOTIFY_STS bit. When the
interrupt is generated, either PIRQB# or SMI# is generated, depending on the value of
the SMB_SMI_EN bit (D31:F3:40h, bit 1). If the HOST_NOTIFY_STS bit is set when this
bit is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or
SMI#) is logically generated by AND’ing the STS and INTREN bits.
0 = Disable
1 = Enable
Bit Description
7:1
DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during
the Host Notify protocol of the SMBus 2.0 Specification. Software should only consider
this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set
to 1.
0 Reserved
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