Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 763

Datasheet 763
PCI Express* Configuration Registers
19.1.9 CLS—Cache Line Size Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
19.1.10 PLT—Primary Latency Timer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
19.1.11 HEADTYP—Header Type Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 0Eh Attribute: RO
Default Value: 81h Size: 8 bits
Bit Description
7:0
Cache Line Size (CLS) — R/W. This is read/write but contains no functionality, per
the PCI Express* Base Specification.
Bit Description
7:3 Latency Count. Reserved per the PCI Express* Base Specification.
2:0 Reserved
Bit Description
7
Multi-Function Device — RO.
0 = Single-function device.
1 = Multi-function device.
6:0
Configuration Layout— RO. This field is determined by bit 2 of the MPC register
(D28:F0-5:Offset D8h, bit 2).
00h = Indicates a Host Bridge.
01h = Indicates a PCI-to-PCI bridge.