Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 764

PCI Express* Configuration Registers
764 Datasheet
19.1.12 BNUM—Bus Number Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 18–1Ah Attribute: R/W
Default Value: 000000h Size: 24 bits
19.1.13 SLT—Secondary Latency Timer
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 1Bh Attribute: RO
Default Value: 00h Size: 8 bits
19.1.14 IOBL—I/O Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 1Ch–1Dh Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
23:16
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number
below the bridge.
15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number the port.
7:0 Primary Bus Number (PBN) — R/W. Indicates the bus number of the backbone.
Bit Description
7:0
Secondary Latency Timer — Reserved for a Root Port per the PCI Express* Base
Specification.
Bit Description
15:12
I/O Limit Address (IOLA) — R/W.
I/O Base bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
11:8
I/O Limit Address Capability (IOLC)
— RO. Indicates that the bridge does not
support 32-bit I/O addressing.
7:4
I/O Base Address (IOBA)
— R/W. I/O Base bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
3:0
I/O Base Address Capability (IOBC)
— RO. Indicates that the bridge does not
support 32-bit I/O addressing.