Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 767

Datasheet 767
PCI Express* Configuration Registers
19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/
F7/F6/F7)
Address Offset: 28h–2Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/
F7/F6/F7)
Address Offset: 2Ch–2Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
19.1.20 CAPP—Capabilities List Pointer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 34h Attribute: RO
Default Value: 40h Size: 8 bits
Bit Description
31:0
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
prefetchable address base.
Bit Description
31:0
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
prefetchable address limit.
Bit Description
7:0
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at 40h in configuration space.