Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 768

PCI Express* Configuration Registers
768 Datasheet
19.1.21 INTR—Interrupt Information Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: See bit description Size: 16 bits
Function Level Reset: No (Bits 7:0 only)
Bit Description
15:8
Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the root port. At
reset, this register takes on the following values that reflect the reset state of the
D28IP register in chipset config space:
NOTE: The value that is programmed into D28IP is always reflected in this register.
7:0
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register. These bits are not reset by FLR.
Port Reset Value
1 D28IP.P1IP
2 D28IP.P2IP
3 D28IP.P3IP
4 D28IP.P4IP
5 D28IP.P5IP
6 D28IP.P6IP
7 D28IP.P7IP
8 D28IP.P8IP