Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 770

PCI Express* Configuration Registers
770 Datasheet
19.1.23 CLIST—Capabilities List Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 40–41h Attribute: RO
Default Value: 8010h Size: 16 bits
19.1.24 XCAP—PCI Express* Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 42h–43h Attribute: R/WO, RO
Default Value: 0042h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT) — RO. Value of 80h indicates the location of the next pointer.
7:0 Capability ID (CID) — RO. Indicates this is a PCI Express* capability.
Bit Description
15:14 Reserved
13:9
Interrupt Message Number (IMN) — RO. The PCH does not have multiple MSI
interrupt numbers.
8
Slot Implemented (SI) — R/WO. Indicates whether the root port is connected to a
slot. Slot support is platform specific. BIOS programs this field, and it is maintained
until a platform reset.
7:4 Device / Port Type (DT) — RO. Indicates this is a PCI Express* root port.
3:0 Capability Version (CV) — RO. Indicates PCI Express 2.0.