Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 771

Datasheet 771
PCI Express* Configuration Registers
19.1.25 DCAP—Device Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 44h–47h Attribute: RO
Default Value: 00008000h Size: 32 bits
Bit Description
31:28 Reserved
27:26 Captured Slot Power Limit Scale (CSPS) — RO. Not supported.
25:18 Captured Slot Power Limit Value (CSPV) — RO. Not supported.
17:16 Reserved
15
Role Based Error Reporting (RBER) — RO. Indicates that this device implements
the functionality defined in the Error Reporting ECN as required by the PCI Express 2.0
specification.
14:12 Reserved
11:9
Endpoint L1 Acceptable Latency (E1AL) — RO. This field is reserved with a setting of
000b for devices other than Endpoints, per the PCI Express 2.0 Spec.
8:6
Endpoint L0s Acceptable Latency (E0AL) — RO. This field is reserved with a setting of
000b for devices other than Endpoints, per the PCI Express 2.0 Spec.
5
Extended Tag Field Supported (ETFS) — RO. Indicates that 8-bit tag fields are
supported.
4:3 Phantom Functions Supported (PFS) — RO. No phantom functions supported.
2:0
Max Payload Size Supported (MPS) — RO. Indicates the maximum payload size
supported is 128B.