PCI Express* Configuration Registers
772 Datasheet
19.1.26 DCTL—Device Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 48h–49h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15 Reserved
14:12 Max Read Request Size (MRRS) — RO. Hardwired to 0.
11
Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-snoop
requests.
10
Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device
connected has detected aux power. It has no effect on the root port otherwise.
9 Phantom Functions Enable (PFE) — RO. Not supported.
8 Extended Tag Field Enable (ETFE) — RO. Not supported.
7:5
Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads,
regardless of the programming of this field.
4 Enable Relaxed Ordering (ERO) — RO. Not supported.
3
Unsupported Request Reporting Enable (URE) — R/W.
0 = The root port will ignore unsupported request errors.
1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control
register when detecting an unmasked Unsupported Request (UR). An ERR_COR is
signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL,
ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-
Advisory UR is received with the severity set by the Uncorrectable Error Severity
register.
2
Fatal Error Reporting Enable (FEE) — R/W.
0 = The root port will ignore fatal errors.
1 = Enables signaling of ERR_FATAL to the Root Control register due to internally
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
1
Non-Fatal Error Reporting Enable (NFE) — R/W.
0 = The root port will ignore non-fatal errors.
1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
0
Correctable Error Reporting Enable (CEE) — R/W.
0 = The root port will ignore correctable errors.
1 = Enables signaling of ERR_CORR to the Root Control register due to internally
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
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