PCI Express* Configuration Registers
774 Datasheet
19.1.28 LCAP—Link Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 4Ch–4Fh Attribute: R/WO, RO
Default Value: See bit description Size: 32 bits
Bit Description
31:24
Port Number (PN) — RO. Indicates the port number for the root port. This value is
different for each implemented port:
23:21 Reserved
20
Link Active Reporting Capable (LARC) — RO. Hardwired to 1 to indicate that this
port supports the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine.
19:18 Reserved
17:15
L1 Exit Latency (EL1) — R/WO.
000b = Less than 1us
001b = 1 us to less than 2 us
010b = 2 us to less than 4 us
011b = 4 us to less than 8 us
100b = 8 us to less than 16 us
101b = 16 us to less than 32 us
110b = 32 us to 64 us
111b = more than 64 us
14:12
L0s Exit Latency (EL0) — RO. Indicates as exit latency based upon common-clock
configuration.
NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5/F6/F7:50h:bit 6
Function Port # Value of PN Field
D28:F0 1 01h
D28:F1 2 02h
D28:F2 3 03h
D28:F3 4 04h
D28:F4 5 05h
D28:F5 6 06h
D28:F6 7 07h
D28:F7 8 08h
LCLT.CCC Value of EL0 (these bits)
0 MPC.UCEL (D28:F0/F1/F2/F3:D8h:bits20:18)
1 MPC.CCEL (D28:F0/F1/F2/F3:D8h:bits17:15)
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