Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 779

Datasheet 779
PCI Express* Configuration Registers
19.1.32 SLCTL—Slot Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 58h–59h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:13 Reserved
12
Link Active Changed Enable (LACE) — R/W. When set, this field enables generation
of a hot plug interrupt when the Data Link Layer Link Active field (D28:F0/F1/F2/F3/F4/
F5/F6/F7:52h:bit 13) is changed.
11 Reserved
10
Power Controller Control (PCC) — RO.This bit has no meaning for module based
Hot-Plug.
9:6 Reserved
5
Hot Plug Interrupt Enable (HPE) — R/W.
0 = Hot plug interrupts based on Hot-Plug events is disabled.
1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events.
4 Reserved
3
Presence Detect Changed Enable (PDE) — R/W.
0 = Hot plug interrupts based on presence detect logic changes is disabled.
1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence
detect logic changes state.
2:0 Reserved.