PCI Express* Configuration Registers
780 Datasheet
19.1.33 SLSTS—Slot Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 5Ah–5Bh Attribute: R/WC, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:9 Reserved
8
Link Active State Changed (LASC) — R/WC.
1 = This bit is set when the value reported in Data Link Layer Link Active field of the
Link Status register (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is changed. In
response to a Data Link Layer State Changed event, software must read Data Link
Layer Link Active field of the Link Status register to determine if the link is active
before initiating configuration cycles to the hot plugged device.
7Reserved
6
Presence Detect State (PDS) — RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5/F6/
F7:42h:bit 8) is set (indicating that this root port spawns a slot), then this bit:
0 = Indicates the slot is empty.
1 = Indicates the slot has a device connected.
Otherwise, if XCAP.SI is cleared, this bit is always set (1).
5 MRL Sensor State (MS) — Reserved as the MRL sensor is not implemented.
4 Reserved
3
Presence Detect Changed (PDC) — R/WC.
0 = No change in the PDS bit.
1 = The PDS bit changed states.
2 MRL Sensor Changed (MSC) — Reserved as the MRL sensor is not implemented.
1 Power Fault Detected (PFD) — Reserved as a power controller is not implemented.
0Reserved
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