Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 781

Datasheet 781
PCI Express* Configuration Registers
19.1.34 RCTL—Root Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 5Ch–5Dh Attribute: R/W
Default Value: 0000h Size: 16 bits
19.1.35 RSTS—Root Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 60h–63h Attribute: R/WC, RO
Default Value: 00000000h Size: 32 bits
Bit Description
15:4 Reserved
3
PME Interrupt Enable (PIE) — R/W.
0 = Interrupt generation disabled.
1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0/F1/F2/F3/F4/
F5/F6/F7:60h, bit 16) is in a set state (either due to a 0 to 1 transition, or due to
this bit being set with RSTS.IS already set).
2
System Error on Fatal Error Enable (SFE) — R/W.
0 = An SERR# will not be generated.
1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5/F6/
F7:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy
of this root port, including fatal errors in this root port.
1
System Error on Non-Fatal Error Enable (SNE) — R/W.
0 = An SERR# will not be generated.
1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5/F6/
F7:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the
hierarchy of this root port, including non-fatal errors in this root port.
0
System Error on Correctable Error Enable (SCE) — R/W.
0 = An SERR# will not be generated.
1 = An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/F5/F6/
F7:04, bit 8) if a correctable error is reported by any of the devices in the hierarchy
of this root port, including correctable errors in this root port.
Bit Description
31:18 Reserved
17
PME Pending (PP) — RO.
0 = When the original PME is cleared by software, it will be set again, the requestor ID
will be updated, and this bit will be cleared.
1 = Indicates another PME is pending when the PME status bit is set.
16
PME Status (PS) — R/WC.
0 = PME was not asserted.
1 = Indicates that PME was asserted by the requestor ID in RID. Subsequent PMEs are
kept pending until this bit is cleared.
15:0
PME Requestor ID (RID) — RO. Indicates the PCI requestor ID of the last PME
requestor. Valid only when PS is set.