Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 783

Datasheet 783
PCI Express* Configuration Registers
19.1.38 LCTL2—Link Control 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 70h–71h Attribute: RO
Default Value: 0001h Size: 16 bits
19.1.39 MID—Message Signaled Interrupt Identifiers Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 80h–81h Attribute: RO
Default Value: 9005h Size: 16 bits
19.1.40 MC—Message Signaled Interrupt Message Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 82–83h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:4 Reserved
3:0
Target Link Speed (TLS)— R/W. This field sets an upper limit on Link operational
speed by restricting the values advertised by the upstream component in its training
sequences.
0001b = 2.5 GT/s Target Link Speed
0010b = 5.0 GT/s and 2.5 GT/s Target Link Speeds
All other values reserved.
Bit Description
15:8 Next Pointer (NEXT) — RO. Indicates the location of the next pointer in the list.
7:0 Capability ID (CID) — RO. Capabilities ID indicates MSI.
Bit Description
15:8 Reserved
7 64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.
6:4
Multiple Message Enable (MME) — R/W. These bits are R/W for software
compatibility, but only one message is ever sent by the root port.
3:1 Multiple Message Capable (MMC) — RO. Only one message is required.
0
MSI Enable (MSIE) — R/W.
0 = MSI is disabled.
1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts.
NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5/F6/F7:04h:bit 2) must be set for an MSI to
be generated. If CMD.BME is cleared, and this bit is set, no interrupts (not even
pin based) are generated.