Datasheet 785
PCI Express* Configuration Registers
19.1.45 PMCAP—Power Management Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A0h–A1h Attribute: RO
Default Value: 0001h Size: 16 bits
19.1.46 PMC—PCI Power Management Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A2h–A3h Attribute: RO
Default Value: C802h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT) — RO. Indicates this is the last item in the list.
7:0
Capability Identifier (CID) — RO. Value of 01h indicates this is a PCI power
management capability.
Bit Description
15:11
PME_Support (PMES) — RO. Indicates PME# is supported for states D0, D3
HOT
and
D3
COLD
. The root port does not generate PME#, but reporting that it does is necessary
for some legacy operating systems to enable PME# in devices connected behind this
root port.
10 D2_Support (D2S) — RO. The D2 state is not supported.
9 D1_Support (D1S) — RO The D1 state is not supported.
8:6
Aux_Current (AC) — RO. Reports 375 mA maximum suspend well current required
when in the D3
COLD
state.
5
Device Specific Initialization (DSI) — RO.
1 = Indicates that no device-specific initialization is required.
4 Reserved
3
PME Clock (PMEC) — RO.
1 = Indicates that PCI clock is not required to generate PME#.
2:0
Version (VS) — RO. Indicates support for Revision 1.1 of the PCI Power Management
Specification.
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