Datasheet 789
PCI Express* Configuration Registers
22
Detect Override (FORCEDET) — R/W.
0 = Normal operation. Detected output from AFE is sampled for presence detection.
1 = Override mode. Ignores AFE detect output and link training proceeds as if a device
were detected.
21
Flow Control During L1 Entry (FCDL1E) — R/W.
0 = No flow control update DLLPs sent during L1 Ack transmission.
1 = Flow control update DLLPs sent during L1 Ack transmission as required to meet the
30 s periodic flow control update.
20:18
Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit
Latency for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/F5/F6/
F7:Offset 50h:bit 6). It defaults to 512 ns to less than 1 µs, but may be overridden by
BIOS.
17:15
Common Clock Exit Latency (CCEL) — R/W. This value represents the L0s Exit
Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/F5/F6/
F7:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden
by BIOS.
14
PCIe Gen2 Speed Disable
0 = PCIe supported data rate is defined as set through Supported Link Speed and
Target Link Speed settings.
1 = PCIe supported data rate is limited to 2.5 GT/s (Gen1). Supported Link Speed
register bits will reflect “0001b” when this bit is set.
When this bit is changed, link retrain needs to be performed for the change to be
effective.
13:8 Reserved
7
Port I/OxApic Enable (PAE) — R/W.
0 = Hole is disabled.
1 = A range is opened through the bridge for the following memory addresses:
6:3 Reserved
Bit Description
Port # Address
1 FEC1_0000h – FEC1_7FFFh
2 FEC1_8000h – FEC1_FFFFh
3 FEC2_0000h – FEC2_7FFFh
4 FEC2_8000h – FEC2_FFFFh
5 FEC3_0000h – FEC3_7FFFh
6 FEC3_8000h – FEC3_FFFFh
7 FEC4_0000h – FEC4_7FFFh
8 FEC4_8000h – FEC4_FFFFh
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