Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 790

PCI Express* Configuration Registers
790 Datasheet
19.1.50 SMSCS—SMI/SCI Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: DCh–DFh Attribute: R/WC
Default Value: 00000000h Size: 32 bits
2
Bridge Type (BT) — R/WO. This register can be used to modify the Base Class and
Header Type fields from the default PCI-to-PCI bridge to a Host Bridge. Having the root
port appear as a Host Bridge is useful in some server configurations.
0 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 04h, and
Header Type = Type 1.
1 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 00h, and
Header Type = Type 0.
1
Hot Plug SMI Enable (HPME) — R/W.
0 = SMI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.
0
Power Management SMI Enable (PMME) — R/W.
0 = SMI generation based on a power management event is disabled.
1 = Enables the root port to generate SMI whenever a power management event is
detected.
Bit Description
Bit Description
31
Power Management SCI Status (PMCS) — R/WC.
1 = PME control logic needs to generate an interrupt, and this interrupt has been
routed to generate an SCI.
30
Hot Plug SCI Status (HPCS) — R/WC.
1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been
routed to generate an SCI.
29:5 Reserved
4
Hot Plug Link Active State Changed SMI Status (HPLAS) — R/WC.
1 = SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5A, bit 8) transitioned from 0-to-1,
and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set. When this bit is
set, an SMI# will be generated.
3:2 Reserved
1
Hot Plug Presence Detect SMI Status (HPPDM) — R/WC.
1 = SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5A, bit 3) transitioned from 0-to-1,
and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set. When this bit is
set, an SMI# will be generated.
0
Power Management SMI Status (PMMS) — R/WC.
1 = RSTS.PS (D28:F0/F1/F2/F3/F4/F5/F6/F7:60, bit 16) transitioned from 0-to-1, and
MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8, bit 1) is set.