High Precision Event Timer Registers
802 Datasheet
20.1.3 GINTR_STA—General Interrupt Status Register
Address Offset: 020h Attribute: R/WC
Default Value: 00000000 00000000h Size: 64 bits
.
20.1.4 MAIN_CNT—Main Counter Value Register
Address Offset: 0F0h Attribute: R/W
Default Value: N/A Size: 64 bits
.
Bit Description
63:8 Reserved. These bits will return 0 when read.
7 Timer 7 Interrupt Active (T07_INT_STS) — R/WC. Same functionality as Timer 0.
6 Timer 6 Interrupt Active (T06_INT_STS) — R/WC. Same functionality as Timer 0.
5 Timer 5 Interrupt Active (T05_INT_STS) — R/WC. Same functionality as Timer 0.
4 Timer 4 Interrupt Active (T04_INT_STS) — R/WC. Same functionality as Timer 0.
3 Timer 3 Interrupt Active (T03_INT_STS) — R/WC. Same functionality as Timer 0.
2 Timer 2 Interrupt Active (T02_INT_STS) — R/WC. Same functionality as Timer 0.
1 Timer 1 Interrupt Active (T01_INT_STS) — R/WC. Same functionality as Timer 0.
0
Timer 0 Interrupt Active (T00_INT_STS) — R/WC. The functionality of this bit
depends on whether the edge or level-triggered mode is used for this timer.
(default = 0)
If set to level-triggered mode:
This bit will be set by hardware if the corresponding timer interrupt is active. Once
the bit is set, it can be cleared by software writing a 1 to the same bit position.
Writes of 0 to this bit will have no effect.
If set to edge-triggered mode:
This bit should be ignored by software. Software should always write 0 to this bit.
NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes
will have no effect.
Bit Description
63:0
Counter Value (COUNTER_VAL[63:0]) — R/W. Reads return the current value of
the counter. Writes load the new value to the counter.
NOTES:
1. Writes to this register should only be done while the counter is halted.
2. Reads to this register return the current value of the main counter.
3. 32-bit counters will always return 0 for the upper 32-bits of this register.
4. If 32-bit software attempts to read a 64-bit counter, it should first halt the counter.
Since this delays the interrupts for all of the timers, this should be done only if the
consequences are understood. It is strongly recommended that 32-bit software only
operate the timer in 32-bit mode.
5. Reads to this register are monotonic. No two consecutive reads return the same
value. The second of two reads always returns a larger value (unless the timer has
rolled over to 0).
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