Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 816

Serial Peripheral Interface (SPI)
816 Datasheet
21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 54h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 58h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Limit.
15:13 Reserved
12:0
Region Base (RB) / Flash Descriptor Base Address Region (FDBAR) — RO. This
specifies address bits 24:12 for the Region 0 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Base.
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
15:13 Reserved
12:0
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.