Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 817

Datasheet 817
Serial Peripheral Interface (SPI)
21.1.10 FREG2—Flash Region 2 (Intel
®
ME) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 5Ch Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
21.1.11 FREG3—Flash Region 3 (GbE) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 60h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
15:13 Reserved
12:0
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 2 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 3 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Limit.
15:13 Reserved
12:0
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 3 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Base