Serial Peripheral Interface (SPI)
836 Datasheet
21.4.4 FADDR—Flash Address Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 08h Attribute: R/W
Default Value: 00000000h Size: 32 bits
21.4.5 FDATA0—Flash Data 0 Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 10h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:25 Reserved
24:0
Flash Linear Address (FLA) — R/W. The FLA is the starting byte linear address of a
SPI Read or Write cycle or an address within a Block for the Block Erase command. The
Flash Linear Address must fall within a region for which BIOS has access permissions.
Bit Description
31:0
Flash Data 0 (FD0) — R/W. This field is shifted out as the SPI Data on the Master-Out
Slave-In Data pin during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin into this register
during the data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, msb to lsb, followed
by the next least significant byte, msb to lsb, etc. Specifically, the shift order on SPI in
terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-31…24
Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0 always
represents the value specified by the cycle address.
Note that the data in this register may be modified by the hardware during any
programmed SPI transaction. Direct Memory Reads do not modify the contents of this
register.
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