EasyManua.ls Logo

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 839

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
936 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Datasheet 839
Serial Peripheral Interface (SPI)
21.4.10 FREG3—Flash Region 3 (GbE) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 60h Attribute: RO
Default Value: 00000000hSize: 32 bits
21.4.11 PR0—Protected Range 0 Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 74h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 3 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Limit.
15:13 Reserved
12:0
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 3 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Base.
Bit Description
31
Write Protection Enable — R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
28:16
Protected Range Limit — R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
15
Read Protection Enable — R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
14:13 Reserved
12:0
Protected Range Base — R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.

Table of Contents

Related product manuals