Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 838

Serial Peripheral Interface (SPI)
838 Datasheet
21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 54h Attribute: RO
Default Value: 00000000h Size: 32 bits
21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 58h Attribute: RO
Default Value: 00000000h Size: 32 bits
21.4.9 FREG2—Flash Region 2 (Intel
®
ME) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 5Ch Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 0 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Limit.
15:13 Reserved
12:0
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 0 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Base.
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 1 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
15:13 Reserved
12:0
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 1 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.
Bit Description
31:29 Reserved
28:16
Region Limit (RL) — RO. This specifies address bits 24:12 for the Region 2 Limit.
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
15:13 Reserved
12:0
Region Base (RB) — RO. This specifies address bits 24:12 for the Region 2 Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base.