Thermal Sensor Registers (D31:F6)
846 Datasheet
22.1.1 VID—Vendor Identification
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bit
Lockable: No Power Well: Core
22.1.2 DID—Device Identification
Offset Address: 02h–03h Attribute: RO
Default Value: 1C24h Size: 16 bits
22.1.3 CMD—Command
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
Bit Description
15:0 Device ID (DID) — RO. Indicates the device number assigned by the SIG.
Bit Description
15:11 Reserved
10
Interrupt Disable (ID) — R/W. Enables the device to assert an INTx#.
0 = When cleared, the INTx# signal may be asserted.
1 = When set, the Thermal logic’s INTx# signal will be deasserted.
9 FBE (Fast Back to Back Enable) — RO. Not implemented. Hardwired to 0.
8 SEN (SERR Enable) — RO. Not implemented. Hardwired to 0.
7 WCC (Wait Cycle Control) — RO. Not implemented. Hardwired to 0.
6 PER (Parity Error Response) — RO. Not implemented. Hardwired to 0.
5VPS (VGA Palette Snoop) — RO. Not implemented. Hardwired to 0.
4 MWI (Memory Write and Invalidate Enable) — RO. Not implemented. Hardwired to 0.
3 SCE (Special Cycle Enable) — RO. Not implemented. Hardwired to 0.
2
BME (Bus Master Enable) — R/W.
0 = Function disabled as bus master.
1 = Function enabled as bus master.
1
Memory Space Enable (MSE) — R/W.
0 = Disable
1 = Enable. Enables memory space accesses to the Thermal registers.
0
IOS (I/O Space) — RO. The Thermal logic does not implement IO Space; therefore,
this bit is hardwired to 0.
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