Datasheet 847
Thermal Sensor Registers (D31:F6)
22.1.4 STS—Status
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0010h Size: 16 bits
22.1.5 RID—Revision Identification
Address Offset: 08h Attribute: RO
Default Value: 00h Size: 8 bits
22.1.6 PI— Programming Interface
Address Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
15
Detected Parity Error (DPE) — R/WC. This bit is set whenever a parity error is seen
on the internal interface for this function, regardless of the setting of bit 6 in the
command register. Software clears this bit by writing a 1 to this bit location.
14 SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.
13 Received Master Abort (RMA) — RO. Not implemented. Hardwired to 0.
12 Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.
11 Signaled Target-Abort (STA) — RO. Not implemented. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEVT) — RO. Does not apply. Hardwired to 0.
8 Master Data Parity Error (MDPE) — RO. Not implemented. Hardwired to 0.
7 Fast Back to Back Capable (FBC) — RO. Does not apply. Hardwired to 0.
6Reserved
5 66 MHz Capable (C66) — RO. Does not apply. Hardwired to 0.
4
Capabilities List Exists (CLIST) — RO. Indicates that the controller contains a
capabilities pointer list. The first item is pointed to by looking at configuration offset
34h.
3
Interrupt Status (IS) — RO. Reflects the state of the INTx# signal at the input of the
enable/disable circuit. This bit is a 1 when the INTx# is asserted. This bit is a 0 after
the interrupt is cleared (independent of the state of the Interrupt Disable bit in the
command register).
2:0 Reserved
Bit Description
7:0 Revision ID (RID) — RO. Indicates the device specific revision identifier.
Bit Description
7:0
Programming Interface (PI) — RO. The PCH Thermal logic has no standard
programming interface.
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