Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 848

Thermal Sensor Registers (D31:F6)
848 Datasheet
22.1.7 SCC—Sub Class Code
Address Offset: 0Ah Attribute: RO
Default Value: 80h Size: 8 bits
22.1.8 BCC—Base Class Code
Address Offset: 0Bh Attribute: RO
Default Value: 11h Size: 8 bits
22.1.9 CLS—Cache Line Size
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
22.1.10 LT—Latency Timer
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
22.1.11 HTYPE—Header Type
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Sub Class Code (SCC) — RO. Value assigned to the PCH Thermal logic.
Bit Description
7:0 Base Class Code (BCC) — RO. Value assigned to the PCH Thermal logic.
Bit Description
7:0 Cache Line Size (CLS) — RO. Does not apply to PCI Bus Target-only devices.
Bit Description
7:0 Latency Timer (LT) — RO. Does not apply to PCI Bus Target-only devices.
Bit Description
7
Multi-Function Device (MFD) — RO. This bit is 0 because a multi-function device
only needs to be marked as such in Function 0, and the Thermal registers are not in
Function 0.
6:0 Header Type (HTYPE) — RO. Implements Type 0 Configuration header.