Datasheet 849
Thermal Sensor Registers (D31:F6)
22.1.12 TBAR—Thermal Base
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
This BAR creates 4K bytes of memory space to signify the base address of Thermal
memory mapped configuration registers. This memory space is active when the
Command (CMD) register Memory Space Enable (MSE) bit is set and either
TBAR[31:12] or TBARH are programmed to a non-zero address. This BAR is owned by
the Operating System, and allows the OS to locate the Thermal registers in system
memory space.
22.1.13 TBARH—Thermal Base High DWord
Address Offset: 14h–17h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
This BAR extension holds the high 32 bits of the 64 bit TBAR. In conjunction with TBAR,
it creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers.
22.1.14 SVID—Subsystem Vendor ID
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
This register should be implemented for any function that could be instantiated more
than once in a given system. The SVID register, in combination with the Subsystem ID
register, enables the operating environment to distinguish one subsystem from the
other(s).
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SID to create one 32-bit write. This register is not
affected by D3
HOT
to D0 reset.
Bit Description
31:12
Thermal Base Address (TBA) — R/W. This field provides the base address for the
Thermal logic memory mapped configuration registers. 4 KB bytes are requested by
hardwiring bits 11:4 to 0s.
11:4 Reserved
3 Prefetchable (PREF) — RO. Indicates that this BAR is NOT pre-fetchable.
2:1
Address Range (ADDRNG) — RO. Indicates that this BAR can be located anywhere
in 64 bit address space.
0 Space Type (SPTYP) — RO. Indicates that this BAR is located in memory space.
Bit Description
31:0 Thermal Base Address High (TBAH) — R/W. TBAR bits 61:32.
Bit Description
15:0 SVID (SVID) — R/WO. These R/WO bits have no PCH functionality.
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