Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 850

Thermal Sensor Registers (D31:F6)
850 Datasheet
22.1.15 SID—Subsystem ID
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
This register should be implemented for any function that could be instantiated more
than once in a given system. The SID register, in combination with the Subsystem
Vendor ID register make it possible for the operating environment to distinguish one
subsystem from the other(s).
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SVID to create one 32-bit write. This register is not
affected by D3
HOT
to D0 reset.
22.1.16 CAP_PTR—Capabilities Pointer
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
22.1.17 INTLN—Interrupt Line
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
22.1.18 INTPN—Interrupt Pin
Address Offset: 3Dh Attribute: RO
Default Value: See description Size: 8 bits
Bit Description
15:0 SID (SAID) — R/WO. These R/WO bits have no PCH functionality.
Bit Description
7:0
Capability Pointer (CP) — RO. Indicates that the first capability pointer offset is
offset 50h (Power Management Capability).
Bit Description
7:0
Interrupt Line — R/W. PCH hardware does not use this field directly. It is used to
communicate to software the interrupt line that the interrupt pin is connected to.
Bit Description
7:4 Reserved
3:0
Interrupt Pin — RO. This reflects the value of the Device 31 interrupt pin bits 27:24
(TTIP) in chipset configuration space.