Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 860

Thermal Sensor Registers (D31:F6)
860 Datasheet
22.2.10 PTA—PCH Temperature Adjust
Offset Address: TBARB+14h Attribute: R/W
Default Value: 0000h Size: 16 bit
22.2.11 TRC—Thermal Reporting Control
Offset Address: TBARB+1Ah Attribute: R/W
Default Value: 0000h Size: 16 bit
Bit Description
15:8
PCH Slope — R/W. This field contains the PCH slope for calculating PCH temperature.
The bits are locked by AE.bit7 (offset 3Fh).
NOTE: When thermal reporting is enabled, BIOS must write DEh into this field.
7:0
Offset— R/W. This field contains the PCH offset for calculating PCH temperature. The
bits are locked by AE.bit7 (offset 3Fh).
NOTE: When thermal reporting is enabled, BIOS must write 87h into this field.
Bit Description
15:13 Reserved
12
Thermal Data Reporting Enable — R/W.
0 = Disable
1 = Enable
11:6 Reserved
5
PCH Temperature Read Enable — R/W
0 = Disables reads of the PCH temperature.
1 = Enables reads of the PCH temperature.
4 Reserved
3
DIMM4 Temperature Read Enable — R/W
0 = Disables reads of DIMM4 temperature.
1 = Enables reads of DIMM4 temperature.
2
DIMM3 Temperature Read Enable — R/W
0 = Disables reads of DIMM3 temperature.
1 = Enables reads of DIMM3 temperature.
1
DIMM2 Temperature Read Enable — R/W
0 = Disables reads of DIMM2 temperature.
1 = Enables reads of DIMM2 temperature.
0
DIMM1 Temperature Read Enable — R/W
0 = Disables reads of DIMM1 temperature.
1 = Enables reads of DIMM1 temperature.