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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
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Datasheet 873
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.1.14 ME_UMA—Management Engine UMA Register
(MEI—D22:F0)
Address Offset: 44h–47h Attribute: RO
Default Value: 80000000h Size: 32 bits
23.1.15 GMES—General ME Status
(MEI—D22:F0)
Address Offset: 48h–4Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
23.1.16 H_GS—Host General Status
(MEI—D22:F0)
Address Offset: 4Ch–4Fh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31
Reserved — RO. Hardwired to 1. Can be used by host software to discover that this
register is valid.
30:7 Reserved
16 ME UMA Size Valid—RO. This bit indicates that FW has written to the MUSZ field.
15:6 Reserved
5:0
ME UMA Size (MUSZ)—RO. This field reflect ME Firmware’s desired size of MEUMA
memory region. This field is set by ME firmware prior to core power bring up allowing
BIOS to initialize memory.
000000b = 0 MB, No memory allocated to MEUMA
000001b = 1 MB
000010b = 2 MB
000100b = 4 MB
001000b = 8 MB
010000b = 16 MB
100000b = 32 MB
Bit Description
31:0 General ME Status (ME_GS)— RO. This field is populated by ME.
Bit Description
31:0
Host General Status(H_GS)— RO. General Status of Host, this field is not used by
Hardware

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Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General IconGeneral
BrandIntel
Model6 SERIES CHIPSET - DATASHEET 01-2011
CategoryController
LanguageEnglish

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