Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 874

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
874 Datasheet
23.1.17 PID—PCI Power Management Capability ID Register
(MEI—D22:F0)
Address Offset: 50h–51h Attribute: RO
Default Value: 6001h Size: 16 bits
23.1.18 PC—PCI Power Management Capabilities Register
(MEI—D22:F0)
Address Offset: 52h–53h Attribute: RO
Default Value: C803h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT) — RO. Value of 60h indicates the location of the next pointer.
7:0
Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management
Register.
Bit Description
15:11
PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the
function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or
D2 which are not supported by Intel MEI.
10:9 Reserved
8:6
Aux_Current (AC) — RO. Reports the maximum Suspend well current required when
in the D3
cold
state. Value of 00b is reported.
5
Device Specific Initialization (DSI) — RO. Indicates whether device-specific
initialization is required.
4Reserved
3 PME Clock (PMEC) — RO. Indicates that PCI clock is not required to generate PME#.
2:0
Version (VS) — RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI
Power Management Specification.