Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
876 Datasheet
23.1.21 MC—Message Signaled Interrupt Message Control Register
(MEI—D22:F0)
Address Offset: 8Eh–8Fh Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
23.1.22 MA—Message Signaled Interrupt Message Address
Register
(MEI—D22:F0)
Address Offset: 90h–93h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
23.1.23 MUA—Message Signaled Interrupt Upper Address Register
(MEI—D22:F0)
Address Offset: 94h–97h Attribute: R/W
Default Value: 00000000h Size: 32 bits
23.1.24 MD—Message Signaled Interrupt Message Data Register
(MEI—D22:F0)
Address Offset: 98h–99h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:8 Reserved.
7
64 Bit Address Capable (C64) — RO. Specifies that function is capable of generating
64-bit messages.
6:1 Reserved
0
MSI Enable (MSIE) — R/W. If set, MSI is enabled and traditional interrupt pins are
not used to generate interrupts.
Bit Description
31:2
Address (ADDR) — R/W. Lower 32 bits of the system specified message address,
always DW aligned.
1:0 Reserved.
Bit Description
31:0
Upper Address (UADDR) — R/W. Upper 32 bits of the system specified message
address, always DW aligned.
Bit Description
15:0
Data (DATA) — R/W. This 16-bit field is programmed by system software if MSI is
enabled. Its content is driven during the data phase of the MSI memory write
transaction.
To Next Page
Loading...
Need help?
General
