Datasheet 877
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.1.25 HIDM—MEI Interrupt Delivery Mode
(MEI—D22:F0)
Address Offset: A0h Attribute: R/W
Default Value: 00h Size: 8 bits
23.1.26 HERES—MEI Extend Register Status
(MEI—D22:F0)
Address Offset: BCh–BFh Attribute: RO
Default Value: 00h Size: 32 bits
Bit Description
7:2 Reserved.
1
MEI Interrupt Delivery Mode (HIDM) — R/W. These bits control what type of
interrupt the Intel MEI will send when ARC writes to set the M_IG bit in AUX space.
They are interpreted as follows:
00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
0
Synchronous SMI Occurrence (SSMIO) — R/WC. This bit is used by firmware to
indicate that a synchronous SMI source has been triggered. Host BIOS SMM handler
can use this bit as status indication and clear it once processing is completed. A write of
1 from host SW clears this status bit.
NOTE: It is possible that an async SMI has occurred prior to sync SMI occurrence and
when the BIOS enters the SMM handler, it is possible that both bit 0 and bit 1 of
this register could be set.
Bit Description
31
Extend Register Valid (ERV).
Set by firmware after all firmware has been loaded. If ERA field is SHA-1, the result of
the extend operation is in HER:5-1. If ERA field is SHA-256, the result of the extend
operation is in HER:8-1.
30
Extend Feature Present (EFP).
This bit is hardwired to 1 to allow driver software to easily detect the chipset supports
the Extend Register FW measurement feature.
29:4 Reserved
3:0
Extend Register Algorithm (ERA).
This field indicates the hash algorithm used in the FW measurement extend operations.
Encodings are:
0h = SHA-1
2h = SHA-256
Other values = Reserved.
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