Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 883
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.2.11 CAPP—Capabilities List Pointer Register
(MEI—D22:F1)
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
23.2.12 INTR—Interrupt Information Register
(MEI—D22:F1)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: 0100h Size: 16 bits
23.2.13 HFS—Host Firmware Status Register
(MEI—D22:F1)
Address Offset: 40h–43h Attribute: RO
Default Value: 00000000h Size: 32 bits
23.2.14 GMES—General ME Status
(MEI—D22:F1)
Address Offset: 48h–4Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
7:0
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
Bit Description
15:8
Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin the Intel MEI host
controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy
interrupt on INTA/INTB/INTC/INTD, respectively.
7:0
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
Bit Description
31:0
Host Firmware Status (HFS) — RO. This register field is used by Firmware to reflect
the operating environment to the host.
Bit Description
31:0 General ME Status (ME_GS)— RO. This field is populated by ME.