Datasheet 89
Signal Description
SATA1GP/GPIO19
Boot BIOS Strap
bit 0
BBS0
Rising edge of
PWROK
This Signal has a weak internal pull-up.
Note: the internal pull-up is disabled after
PLTRST# deasserts. This field determines the
destination of accesses to the BIOS memory
range. Also controllable using Boot BIOS
Destination bit (Chipset Config Registers: Offset
3410h:Bit 10). This strap is used in conjunction
with Boot BIOS Destination Selection 1 strap.
NOTES:
1. If option 00 (LPC) is selected, BIOS may
still be placed on LPC, but all platforms
are required to have SPI flash connected
directly to the PCH's SPI bus with a valid
descriptor in order to boot.
2. Booting to PCI is intended for debut/
testing only. Boot BIOS Destination
Select to LPC/PCI by functional strap or
using Boot BIOS Destination Bit will not
affect SPI accesses initiated by
Management Engine or Integrated GbE
LAN.
3. PCI Boot BIOS destination is not
supported on mobile.
GNT2#/ GPIO53 Reserved
Rising edge of
PWROK
This Signal has a weak internal pull-up.
NOTES:
1. The internal pull-up is disabled after
PLTRST# deasserts.
2. This signal should not be pulled low.
HDA_SDO
Flash Descriptor
Security
Override / Intel
ME Debug Mode
Rising edge of
PWROK
Signal has a weak internal pull-down.
If strap is sampled low, the security measures
defined in the Flash Descriptor will be in effect
(default) If sampled high, the Flash Descriptor
Security will be overridden.
This strap should only be asserted high using
external pull-up in manufacturing/debug
environments ONLY.
NOTES:
1. The weak internal pull-down is disabled
after PLTRST# deasserts.
2. Asserting the HDA_SDO high on the
rising edge of PWROK will also halt Intel
®
Management Engine after chipset bring
up and disable runtime Intel ME features.
This is a debug mode and must not be
asserted after manufacturing/debug.
Table 2-27. Functional Strap Definitions (Sheet 3 of 5)
Signal Usage
When
Sampled
Comment
Bit11 Bit 10
Boot BIOS
Destination
01 Reserved
10 PCI
11 SPI
00 LPC
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