Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Signal Description
90 Datasheet
DF_TVS
DMI and FDI Tx/
Rx Termination
Voltage
Rising edge
of PWROK
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
GPIO28
On-Die PLL
Voltage
Regulator
Rising edge of
RSMRST# pin
This signal has a weak internal pull-up.
NOTE: The internal pull-up is disabled after
RSMRST# deasserts.
The On-Die PLL voltage regulator is enabled
when sampled high. When sampled low the On-
Die PLL Voltage Regulator is disabled.
HDA_SYNC
On-Die PLL
Voltage
Regulator
Voltage Select
Rising edge of
RSMRST# pin
This signal has a weak internal pull-down.
On Die PLL VR is supplied by 1.5 V from VccVRM
when sampled high, 1.8 V from VccVRM when
sampled low.
GPIO15
TLS
Confidentiality
Rising edge of
RSMRST# pin
Low = Intel ME Crypto Transport Layer Security
(TLS) cipher suite with no confidentiality
High = Intel ME Crypto TLS cipher suite with
confidentiality
This signal has a weak internal pull-down.
NOTES:
1. The weak internal pull-down is disabled
after RSMRST# deasserts.
2. A strong pull-up may be needed for GPIO
functionality
3. This signal must be pulled up to support
Intel AMT with TLS. Intel ME
configuration parameters also need to be
set correctly to enable TLS.
L_DDC_DATA LVDS Detected
Rising edge of
PWROK
When ‘1’- LVDS is detected; When ‘0’- LVDS is
not detected.
NOTE: This signal has a weak internal pull-
down. The internal pull-down is disabled
after PLTRST# deasserts.
SDVO_CTRLDATA Port B Detected
Rising edge of
PWROK
When ‘1’- Port B is detected; When ‘0’- Port B is
not detected
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
DDPC_CTRLDATA Port C Detected
Rising edge of
PWROK
When ‘1’- Port C is detected; When ‘0’- Port C is
not detected
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
DDPD_CTRLDATA Port D Detected
Rising edge of
PWROK
When ‘1’- Port D is detected; When ‘0’- Port D is
not detected
This signal has a weak internal pull-down.
NOTE: The internal pull-down is disabled after
PLTRST# deasserts.
DSWVRMEN
Deep S4/S5 Well
On-Die Voltage
Regulator Enable
Always
If strap is sampled high, the Integrated Deep
S4/S5 Well (DSW) On-Die VR mode is enabled.
Table 2-27. Functional Strap Definitions (Sheet 4 of 5)
Signal Usage
When
Sampled
Comment

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General

Brand	Intel
Model	6 SERIES CHIPSET - DATASHEET 01-2011
Category	Controller
Language	English