Datasheet 895
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.5.1 VID—Vendor Identification Register (IDER—D22:F2)
Address Offset: 00–01h Attribute: RO
Default Value: 8086h Size: 16 bits
23.5.2 DID—Device Identification Register (IDER—D22:F2)
Address Offset: 02–03h Attribute: RO
Default Value: See bit description Size: 16 bits
23.5.3 PCICMD— PCI Command Register (IDER—D22:F2)
Address Offset: 04–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:0 Vendor ID (VID) — RO. This is a 16-bit value assigned by Intel.
Bit Description
31:16
Device ID (DID) — RO. This is a 16-bit value assigned to the PCH IDER controller.
See the Intel
®
6 Series Chipset Specification Update for the value of the DID
Register.
Bit Description
15:11 Reserved
10
Interrupt Disable (ID)—R/W. This disables pin-based INTx# interrupts. This bit
has no effect on MSI operation. When set, internal INTx# messages will not be
generated. When cleared, internal INTx# messages are generated if there is an
interrupt and MSI is not enabled.
9:3 Reserved
2
Bus Master Enable (BME)—RO. This bit controls the PT function's ability to act as a
master for data transfers. This bit does not impact the generation of completions for
split transaction commands.
1
Memory Space Enable (MSE)—RO. PT function does not contain target memory
space.
0
I/O Space enable (IOSE)—RO. This bit controls access to the PT function's target
I/O space.
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